This application relates to integrated circuits (“ICs”). More particularly, this application relates to loopback testing for ICs.
Efficient testing of ICs is a key challenge in the semiconductor industry. Typically, a relatively large number of ICs may need to be automatically tested within a relatively short period of time. The tests can be used, for example, to identify defective ICs which are subsequently discarded.
Automated testing of ICs has traditionally been performed after the IC has been diced from its wafer and packaged in various materials (e.g., plastic). The packaged IC would be automatically placed into a customized holder (“socket”) that was electrically coupled to input/output (“I/O”) pins of the IC for testing. However, many modern ICs are used without a package and are mounted directly on a circuit board. Such unpackaged ICs provide lower cost of manufacture and reduced consumption of circuit board area. Unfortunately, these unpackaged ICs can be significantly more difficult to test than packaged ICs.
For example, it can be very difficult and costly to build sockets for holding unpackaged ICs. As a result, these ICs are typically tested while they reside on an undiced wafer using specially-designed probes. Unfortunately, these probes often require relatively large openings on the tested ICs and a relatively large number of signal lines (e.g., to support companion ground lines), especially when the test signals contain radio-frequency (“RF”) content. As such, the area requirements can make them impractical, and sometimes impossible, to use with many modern ICs.
In view of the foregoing, it would be desirable to provide methods and apparatus for efficient wafer-level testing of ICs. Furthermore, it would be desirable to achieve such wafer-level testing with relatively low additional area and complexity.